Home
last modified time | relevance | path

Searched hist:"84 a01de5ce080ac9cdd243d9d64da2df0ae9cb77" (Results 1 – 8 of 8) sorted by relevance

/libCEED/backends/blocked/
H A Dceed-blocked.hdiff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
H A Dceed-blocked.cdiff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
/libCEED/backends/avx/
H A Dceed-avx-blocked.c84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
H A Dceed-avx-serial.c84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
/libCEED/backends/ref/
H A Dceed-ref.hdiff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
H A Dceed-ref-basis.cdiff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
/libCEED/
H A DREADME.mddiff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style
H A DMakefilediff 84a01de5ce080ac9cdd243d9d64da2df0ae9cb77 Tue Mar 12 16:15:08 UTC 2019 Jeremy L Thompson <25011573+jeremylt@users.noreply.github.com> Serial and Blocked AVX Backends (#198)

* Add serial AVX backend

* Style and README changes

* Simplify AVX serial tensor loop

* Minor performance improvement

* C=1 AVX scalar case

* Increase use of AVX commands for edge cases

* Prep for eventual Tensor Object

* Comment updates

* Readme update

* Update README

* Refactor to reduce code

* Increase vectorization in remainder of columns

* Vectorize column remainder on C=1 case

* Switch to static inlining for AVX tensor contract

* Tidying for merge

* make style

* Style cleanup

* Full register use for columns

* Make style