147d993e7Ssuyashtn /* Portions of this code are under: 247d993e7Ssuyashtn Copyright (c) 2022 Advanced Micro Devices, Inc. All rights reserved. 347d993e7Ssuyashtn */ 459194e33SJacob Faibussowitsch #ifndef __MPIHIPSPARSEMATIMPL 547d993e7Ssuyashtn #define __MPIHIPSPARSEMATIMPL 647d993e7Ssuyashtn 76d54fb17SJacob Faibussowitsch #include <petscpkg_version.h> 847d993e7Ssuyashtn #if PETSC_PKG_HIP_VERSION_GE(5, 2, 0) 947d993e7Ssuyashtn #include <hipsparse/hipsparse.h> 1047d993e7Ssuyashtn #else 1147d993e7Ssuyashtn #include <hipsparse.h> 1247d993e7Ssuyashtn #endif 136d54fb17SJacob Faibussowitsch #include <petsc/private/veccupmimpl.h> 1447d993e7Ssuyashtn 1547d993e7Ssuyashtn struct Mat_MPIAIJHIPSPARSE { 1647d993e7Ssuyashtn /* The following are used by GPU capabilities to store matrix storage formats on the device */ 17*2c4ab24aSJunchao Zhang MatHIPSPARSEStorageFormat diagGPUMatFormat = MAT_HIPSPARSE_CSR; 18*2c4ab24aSJunchao Zhang MatHIPSPARSEStorageFormat offdiagGPUMatFormat = MAT_HIPSPARSE_CSR; 1947d993e7Ssuyashtn }; 2047d993e7Ssuyashtn 2147d993e7Ssuyashtn #endif 22